Robert M. Radway

Robert M. Radway

Assistant Professor of Electrical & Systems Engineering

Publications

Journal Publications

  1. L. Yang, R.M. Radway, Y.-H. Chen, T.F. Wu, H. Liu, E. Ansari, V. Chandra, S. Mitra, E. Beigné, “Three-Dimensional Stacked Neural Network Accelerator Architectures for AR/VR Applications,” in IEEE Micro, vol. 42, no. 6, pp. 116-124, 1 Nov.-Dec. 2022.
  2. Equally Contributing†: K. Prabhu†, A. Gural†, Z. F. Khan†, R.M. Radway†, M. Giordano, K. Koul, R. Doshi, J.W. Kustin, T. Liu, M.-F. Chang, G. Lallement, B. Murmann, S. Mitra, P. Raina., “CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2Mbyte On-Chip Foundry Resistive RAM for Efficient Training and Inference,” in IEEE Journal of Solid-State Circuits (JSSC), vol. 57., no. 4, pp. 1013-1026, April 2022.
  3. B.Q. Le, A. Levy, T.F. Wu, R.M. Radway, E.R. Hsieh, X. Zheng, M. Nelson, P. Raina, H.-S.P. Wong, S. Wong, S. Mitra, “RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays,” in IEEE Transactions on Electron Devices, vol. 68, no. 9, pp. 4397-4403, July 2021.
  4. E.R. Hsieh, X. Zheng, B. Q. Le, Y. C. R.M. Radway, M. Nelson, H.-S.P. Wong, S. Mitra and S. Wong, “Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array,” in IEEE Electron Device Letters, vol. 42, no. 3, pp. 335-338, March 2021.
  5. R.M. Radway, A. Bartolo, P.C. Jolly, Z.F. Khan, B.Q. Le, P. Tandon, T.F. Wu, Y. Xin, E. Vianello, P. Vivet, E. Nowak, H.-S.P. Wong, M.M.S. Aly, E. Beigne, M. Wootters, S. Mitra, “Illusion of large on-chip memory by networked computing chips for neural network inference,” in Nature Electronics, 4, 71-80 (2021).

Conference Publications and Abstracts

  1. T. Srimani, A. Bechdolt, S. Choi, C. Gilardi, A. Kasperovich, S. Li, Q. Lin, M. Malakoutian, P. McEwen, R.M. Radway, D. Rich, A.C. Yu, S. Fuller, S. Achour, S. Chowdhury, H.-S.P. Wong, M.M. Shulaker, S. Mitra, “N3XT 3D Technology Foundations and Their Lab-to-Fab: Omni 3D Logic, Logic+Memory Ultra-Dense 3D, 3D Thermal Scaffolding,” 2023 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2023.
  2. A. Wei, A. Levy, P.(L.) Yi, R.M. Radway, P. Raina, S. Mitra, S. Achour, “PBA: Percentile-Based Level Allocation for Multiple-Bits-Per-Cell RRAM,” 2023 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Francisco, CA, USA, 2023.
  3. D. Rich, A. Kasperovich, M. Malakoutian, R. M. Radway, S. Hagiwara, T. Yoshikawa, S. Chowdhury, S. Mitra, “Thermal Scaffolding for Ultra-Dense 3D Integrated Circuits,” 2023 60th ACM/IEEE Design Automation Conference (DAC), San Francisco, CA, USA, 2023, pp. 1-6.
  4. Equally Contributing†: T. Srimani†, A.C. Yu†, R.M. Radway†, D.T. Rich, M. Nelson, S. Wong, D. Murphy, S. Fuller, G. Hills, S. Mitra, M.M. Shulaker, “Foundry Monolithic 3D BEOL Transistor + Memory Stack: Iso-performance and Iso-footprint BEOL Carbon Nanotube FET+RRAM vs. FEOL Silicon FET+RRAM,” 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2023, pp. 1-2.
  5. Equally Contributing†: T. Srimani†, R.M. Radway†, J. Kim^, K. Prabhu, D. Rich, C. Gilardi, P. Raina, M. Shulaker, S.K. Lim, S. Mitra, “Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large Benefits,” 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), Antwerp, Belgium, 2023, pp. 1-6.
  6. L.R. Upton, G. Lallement, M. D Scott, J. Taylor, R.M. Radway, D. Rich, M. Nelson, S. Mitra, B. Murmann., “Testbench on a Chip: A Yield Test Vehicle for Resistive Memory Devices,” 2023 24th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2023, pp. 1-7.
  7. R.M. Radway, K. Sethi, W.-C. Chen, J. Kwon, S. Liu, T.F. Wu, E. Beigne, M.M. Shulaker, H.-S.P. Wong, S. Mitra, “The Future of Hardware Technologies for Computing: N3XT 3D MOSIAC, Illusion Scaleup, Co-Design (Invited),” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2021.
  8. Circuits Best Student Paper Award – Equally Contributing†: M. Giordano†,K. Prabhu†, K. Koul†, R.M. Radway†, A. Gural†, R. Doshi†, Z.F. Khan, J.W. Kustin, T. Liu, G.B. Lopes, V. Turbiner, W.-S. Khwa, Y.-D. Chih, M.-F. Chang, G. Lallement†, B. Murmann, S. Mitra, P. Raina, “CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2Mbyte On-Chip Foundry Resistive RAM for Efficient Training and Inference,” Symposium on VLSI Circuits, pg. 1-2, June 2021.
  9. E.R. Hsieh, M. Giordano, B. Hodson, A. Levy, S.K. Osekowsky, R.M. Radway, Y.C. Shih, W. Wan, T.F. Wu, X. Zheng, M. Nelson, B.Q. Le, H.-S.P. Wong, S. Mitra and S. Wong, “High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning,” IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, Dec. 2019.
  10. T.F. Wu, B.Q. Le, R.M. Radway, A. Bartolo, W. Hwang, S. Jeong, H. Li, P. Tandon, E. Vianello, P. Vivet, E. Nowak, M.K. Wootters, H.-S.P. Wong, M.M.S. Aly, E. Beigne, S. Mitra, “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques,” 2019 IEEE International Solid- State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 226-228.
  11. R.M. Radway, K.R. Bagnall, E.N. Wang, T. Palacios. “Near Junction Thermal Management of GaN-on-SiC HEMTs via Wafer Bonding,” 2016 International Workshop on Nitride Semiconductors (IWN), Orlando, FL, USA, 2016, pp. 218.

Presentations & Posters

  1. R.M. Radway, T. Srimani, “New Iso-performance Foundry Monolithic 3D Transistor+Memory Unlocks Large Benefits vs. Conventional Silicon Transistor+Memory within the Same Footprint”, Stanford SystemX Fall Conference, Stanford, CA, November 2023.
  2. R.M. Radway, “MINOTAUR Illusion: Transformer Edge Inference and Training that Scale Across Single- and Multi-Chip Systems”, Stanford SystemX Fall Conference, Stanford, CA, November 2023.
  3. R.M. Radway, S. Mitra, R. Howe, “NanoSystems for Abundant Data Computing”, Samsung-Stanford Research Initiative Workshop, Stanford, CA, September 2023.
  4. R.M. Radway, K. Prabhu, S. Mitra, P. Raina, “MINOTAUR: Transformer Edge Inference and Training that Scale Across Single- and Multi-Chip Systems”, TSMC Corporate Research Seminar Series, Virtual, May 2023.
  5. R.M. Radway, C. Gilardi, T. Srimani, “Ultra-Dense 3D Physical Design Unlock New Architectural Design Points with Large Benefits”, SLAC Nano/Micro Workshop, Stanford, CA, May 2023.
  6. R.M. Radway, M. Giordano, “CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference”, Samsung Metaverse Workshop, San Jose, CA, April 2023.
  7. R.M. Radway, T. Srimani, “Foundry Monolithic 3D Technology Enables New Architectural Design Points with Large Benefits”, Stanford SystemX Fall Conference, Stanford, CA, November 2022.
  8. R.M. Radway, F. Peddinghaus, A. Symons, “Emulating Illusion Scaleup of 3D MOSAICs”, Robust Systems Group Seminar, Stanford, CA, November 2022.
  9. R.M. Radway, S. Mitra, “Illusion and Illusion Scaleup for 3D MOSAIC”, ACCESS Seminar Series, Virtual, June 2022.
  10. R.M. Radway, M. Giordano, “CHIMERA: A 0.92 TOPS, 2.2 TOPS/W Edge AI Accelerator with 2 MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference”, Stanford System X Fall Conference, Virtual, November 2021.
  11. R.M. Radway, Y.-N. Wang, “The Future of Hardware Technologies for Computing: N3XT 3D MOSAIC and Illusion Scaleup,” Robust Systems Group Seminar, Stanford, CA, November, 2021.
  12. S. Mitra, R.M. Radway, “21st-Century NanoSystems for Abundant-Data Computing”, ACESS Seminar Series, Virtual, June 2021.
  13. R.M. Radway, “Illusion of Large On-Chip Memory for Neural Network Inference”, SystemX Fall Conference, Stanford, CA, November 2020.
  14. R.M. Radway, “Illusion of Large On-Chip Memory for Neural Network Inference”, Robust Systems Group Seminar, Stanford, CA, November 2020.
  15. R.M. Radway, “Illusion of Large On-Chip Memory for Neural Network Inference”, TSMC, Hsinchu, Taiwan, February 2020.
  16. R.M. Radway, “Creating the Illusion of Large On-Chip Memory”, Robust And Testable Systems Seminar, Stanford, CA, January 2020.
  17. R.M. Radway, “Illusion of Large On-Chip Memory for Neural Network Inference”, Xilinx, San Jose, CA, November 2019.
  18. R.M. Radway, “N3XT Heterogenous Integration: From Lab to Fab”, Stanford SystemX Fall Conference, Stanford, CA, November 2019.
  19. R.M. Radway, “Abundant Data Computing: The N3XT 1,000x”, Google, Mountain View, CA, October 2019.
  20. R.M. Radway, S. Mitra “RRAM Integrated on Silicon CMOS for AI Applications”, Emerging Memory and Artificial Intelligence Workshop, Stanford, CA, August 2019.
  21. R.M. Radway, A. Bartolo “Abundant Data Computing: The N3XT 1,000x”, ARM, San Jose, CA, May 2019.
  22. T.F. Wu, B.Q. Le, R.M. Radway, et al. “A 43pJ/Cycle Non-Volatile Microcontroller with 4.7μs Shutdown/Wake-up Integrating 2.3-bit/Cell Resistive RAM and Resilience Techniques,” Facebook, Menlo Park, CA, April 2018.
  23. R.M. Radway and M. Lee, “Compute Immersed in Memory: Analytical Performance Models for Multi-Chip Nanosystems”, Robust and Testable Systems Seminar, Stanford, CA, November 2018.
  24. R.M. Radway “Fast Algorithms for Synapse Detection,” SuperUROP Final Presentations, MIT, Cambridge, MA, Apr 2015.
  25. R.M. Radway “Fast Algorithms for Automated Synapse Detection,” SuperUROP Poster Session, MIT, Cambridge, MA, Dec 2014.

Book Chapters

  1. D. Rich, A. Bartolo, C. Gilardo, B.Q. Le, H. Li, R. Park, R. M. Radway, M.M.S. Aly, H.-S.P. Wong, S. Mitra, “Heterogeneous 3D Nano-systems: The N3XT Approach?”. In: Murmann B., Hoefflinger B. (eds) NANO-CHIPS 2030, Springer 2020.

Master’s Thesis

  1. R.M. Radway, “Near junction thermal management of GaN HEMTs via wafer bonding,” Master’s thesis, Massachusetts Institute of Technology, 2017, https://dspace.mit.edu/handle/1721.1/113116.